This invention relates to a method and apparatus for transmitting digital data.
As an interfacing standard supporting high-speed data transfer and real-time transfer, with a view to interfacing for data transfer, there is known the IEEE 1394 high-Performance Serial Bus Standard (IEEE 1394 standard).
This IEEE 1394 standard provides data transfer speeds at 100 Mbps (98.304 Mbps), 200 Mbps (196.608 Mbps) and 400 Mbps (393.216 Mbps). The 1394 port, having an upper order transfer speed, is prescribed to maintain compatibility with respect to its lower order transfer speed. Thus, the data transfer speeds of 100 Mbps, 200 Mbps and 400 Mbps can co-exist on the same network. Also, in the IEEE 1394 standard, a transfer format of the DS-LINK (DATA/STROBE LINK) encoding system is used, in which transfer data are converted into data signals and strobe signals supplementing the data signals, as shown in FIG. 1, and in which clock signals are generated by taking an exclusive OR of the two signals. Referring to the cable structure shown in a cross-sectional view of FIG. 2, there is prescribed a cable 200 of a structure in which a cable obtained on bundling two sets of twist pair lines (signal lines) 202 shielded by first shield layers 201 and power source lines 203 is further shielded by a second shield layer 204.
In the connection system of the IEEE 1394 standard, two types of systems, namely a daisy chain system and a node branched system, may be used. With the daisy chain system, up to a maximum of 16 nodes (an equipment having the 1394 port) can be connected, with the maximum length between the nodes being 4.5 m. By using node branching in combination, as shown in FIG. 3, it is possible to connect up to 63 nodes possible with the standard (physical node addresses).
With the IEEE 1394 standard, connection or disconnection of the above-described cable can be performed with the equipment remaining in operation, that is in the power up state, so that the 1394 network can be re-constructed automatically at a time point of node addition or deletion. The equipment of the node connected at this time can be recognized automatically. The ID or layout of the connected equipments can be managed on the interface.
The constituent elements of the interface conforming to the IEEE 1394 standard as well as the protocol architecture are shown in FIG. 4. The interface of the IEEE 1394 can be classified into the hardware and the firmware.
The hardware is made up of a physical layer (PHY) and a linked layer (link layer).
In the physical layer, signals of the IEEE 1394 standard are driven directly. The link layer has the host interface and the physical layer.
The firmware includes a transaction layer, made up of a management driver for performing actual operations for the interface conforming to the IEEE 1394 standard, and a management layer, made up of a driver for network management conforming to the IEEE 1394 standard, termed Serial Bus management (SBM).
The application layer includes a software used by the user and a management software for interfacing the management layer or the transaction layer.
In the IEEE 1394 standard, the operation of transfer performed in the network is termed a sub-action, for which the following two sorts of the sub-action are prescribed. That is, as the two sub-actions, an asynchronous transmission mode, termed xe2x80x9casynchronousxe2x80x9d, and a synchronous transfer mode guaranteeing a transfer area, termed xe2x80x9cisochronousxe2x80x9d, are defined. Each sub-action is divided into three parts, and assumes the transfer states termed xe2x80x9carbitrationxe2x80x9d,xe2x80x9cpacket transmissionxe2x80x9d and xe2x80x9cacknowledgmentxe2x80x9d.
In the asynchronous sub-action, asynchronous transfer is used. In FIG. 5, showing the temporal transition state in the transfer mode, the first sub-action gap specifies the idle state of the bus. By monitoring the sub-action gap time, the directly previous transfer comes to a close and judgment is given as to whether or not new transfer is possible.
If the idle state continues for longer than a preset time duration, a decision is given that a node desiring the transfer can use a bus, and arbitration is executed in order to acquire a bus control right. A decision to stop a bus actually is given by a node B positioned at a root, as shown in FIGS. 6a and 6b. The node which has acquired the bus control right by this arbitration then executes data transfer, that is packet transmission. After the data transfer, a node which has received data returns a code ack (code returned to acknowledge the reception) responsive to the received result for the transferred data to execute response acknowledgement. By executing this acknowledgement, both the transmission and receiving nodes can confirm by the ack contents that transfer has been completed regularly.
The sub-action gap, that is the bus idle state, is then resumed to repeat the above transfer operation.
In the isochronous sub-action, transfer of a structure basically similar to the asynchronous transfer is executed. This transfer is executed in preference to the asynchronous transfer in the asynchronous sub-action, as shown in FIG. 7. This isochronous transfer in the isochronous sub-action is executed in preference to asynchronous transfer in the asynchronous sub-action approximately every 8 kHz to set a transfer mode which guarantees a transfer area. This realizes transfer of real-time data.
If isochronous transfer of real-time data is to be executed simultaneously in plural nodes, a channel ID for distinguishing the contents (transmission node) is set in the transfer data in order to receive only the required real-time data.
The physical layer in the above-described IEEE 1394 standard is made up of a physical layer logical block (PHY LOGIC) 102, a selector block (RXCLOCK/DATA SELECTOR) 103, port logic blocks (PORT LOGIC 1, PORT LOGIC 2, PORT LOGIC 3), 104, 105, 106, cable ports (CABLE PORT 1, CABLE PORT 2, CABLE PORT 3) 107, 108, 109 and a clock generating block (PLL) 110, as shown in FIG.8.
The physical layer logical block 102 performs I/O control and arbitration control with the link layer in the IEEE 1394 standard and is connected not only to a link layer controller 100 but also to the selector block 103 and to the port logic ports 104, 105, 106.
The selector block 103 selects data (DATA 1, DATA 2, DATA 3) received via logical blocks 104, 105, 106, connected to the cable ports 107, 108, 109, and reception clocks (RXCLK 1, RXCLK 2, RXCLK 3), and is connected to the physical layer logical block 102 and to the port logic ports 104, 105, 106.
For reception, each set of packet data DATA 1, DATA 2, DATA 3 received via the port logic ports 104, 105, 106 and the reception clocks (RXCLK 1, RXCLK 2, RXCLK 3) is selected to send the received packet data and the reception clocks via cable ports 107, 108, 109 to the physical layer logical block 102. If, for example, the packet data DATA 1 received via the port logical block 104 via cable port 107 and the reception clock RXCLK 1 are selected, the received packet data (DATA 1) and its reception clock RXCLK 1 are sent by the port logical block 104 to the physical layer logical block 102. The packet data selected by the selector block 103 is written by the reception clock in a FIFO memory in the physical layer logical block 102. The packet data written in the FIFO memory is read out by a system clock SYSCLK provided by a clock generating block 110.
The port logical block 104 sends/receives an arbitration signal (ARB.SIGNAL) and data (DATA 1) via cable port 107 and has the function of generating reception clocks (RXCLK 1) from the data signals sent via cable port 107 and its strobe signals. This port logical block 104 is fed during arbitration with an arbitration signal (ARB. SIGNAL) from the physical layer logical block 102.
During data transmission time, the port logical block 104 converts the packet data DATA 1 sent via selector block 103 from the physical layer logical block 102 with transmission clocks TXCLK provided by the clock generating block 110 into serial data which is sent over the cable port 107.
During data reception, the port logical block 104 sends the packet data DATA 1 received over the cable port 107 to the physical layer logical block 102 over the selector block 103 along with the reception clocks (RXCLK 1). If the port logical block 104 is selected by the selector block 103, the packet data (DATA 1) is written in the FIFO memory in the physical layer logical block 102.
The port logical block 105 sends/receives the arbitration signal(ARB. SIGNAL) and data (DATA 2) over a cable port 108 and has the function of generating reception clocks (RXCLK 2) from the data signals sent via cable port 108 and its strobe signals. This port logical block 105 is fed during arbitration with an arbitration signal (ARB. SIGNAL) from the physical layer logical block 102.
During the data transmission time, the port logical block 105 converts the packet data (DATA 2) sent from the physical layer logical block 102 via the selector block 103 by the transmission clocks (TXCLK) provided by the clock generating block 110 into serial data which is sent via cable port 108.
During data reception time, this port logical block 105 sends the packet data (DATA 2) sent from the physical layer logical block 102 over the cable port 108 via selector block 103 to the physical layer logical block 102 along with the reception clocks (RXCLK 2). If this physical layer logical block 102 has been selected by the selector block 103, the packet data (DATA 2) is written by the reception clocks (RXCLK 2) in the FIFO memory in the physical layer logical block 102.
The port logical block 106 sends/receives the arbitration signal (ARB. SIGNAL) and data (DATA 3) over a cable port 108 and has the function of generating reception clocks (RXCLK 3) from the data signals sent via cable port 109 and its strobe signals. This port logical block 106 is fed during arbitration with an arbitration signal (ARB. SIGNAL) from the physical layer logical block 102.
During the data transmission time, the port logical block 106 converts the packet data (DATA 3) sent from the physical layer logical block 102 via the selector block 103 by the transmission clocks (TXCLK) provided by the clock generating block 110 into serial data which is sent via cable port 109.
During data reception time, this port logical block 106 sends the packet data (DATA 3) received via the cable port 109 and via selector block 103 to the physical layer logical block 102 along with the reception clocks (RXCLK 2). If this port logical block 104 has been selected by the selector block 103, the packet data (DATA 1) is written by the reception clocks (RXCLK 1) in the FIFO memory in the physical layer logical block 102.
The cable port 107 drives a twisted paired cable with a signal sent from the port logical block 104, while converting level of the signal sent over the twisted paired cable to send the converted signal to the port logical block 104.
The cable port 108 drives the twisted paired cable with a signal sent from the port logical block 105, while converting level of the signal sent over the twisted paired cable to send the converted signal to the port logical block 105.
The cable port 109 drives the twisted paired cable with a signal sent from the port logical block 106, while converting level of the signal sent over the twisted paired cable to send the converted signal to the port logical block 106.
The clock generating block 110 generates system clocks (SYSCLK) of 49.152 MHz and transmission clocks (TXCLK) of 98.304 MHz from clocks of 24.576 MHz provide by a quartz oscillator 111.
The logical values of the arbitration signal in the physical layer are three values of xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d and xe2x80x9cZxe2x80x9d, and are generated in accordance with the rule shown in Tables 1 and 2, while being decoded in accordance with the rule shown in Table 3. The value xe2x80x9cZxe2x80x9d denotes an inoperative state of a driver.
Of the two sets of the twist pair lines 202, one set of the twist pair lines TPA/TPA* sends a strobe signal (STRB_TX), while receiving the strobe signal (STRB_RX). The signals STRB_TX, DATA_TX, STRB_ENABLE and DATA_ENABLE are used for generating arbitration signals (ARB_A_RX, ARB_B_RX).
Also, in the physical layer, two transmission arbitration signals (ABR_A_TX, ARB_B_TX) are encoded to the line states, using the rule shown in Table 4. These states have different meanings depending on whether signals are sent to a parent node or to the child node, as shown in Table 4.
The parent-child relation in the IEEE 1394 standard is explained. Of the plural nodes connected to the network, there exist several nodes present at an end (leaf). Directly after resetting, each node checks whether or not it itself is a leaf. Whether each node is a leaf is checked by recognition of how many cables are connected to the node itself. Specifically, a node having a sole port or a node having plural ports only one of which is connected is a node. Each leaf makes an inquiry to a node to which it is connected (parent node). The node receiving the inquiry accepts the inquiring node to which it is connected as being a child. A further inquiry is made to a destination of connection from a node for which the parent-child relation has not been set. In this manner, the parent-child relation in the network is set. Finally, the node whose ports in their entirety serve as parent serves as a root.
In the physical layer, the interpolation arbitration signals (ARB_A, ARB_B) are decoded to the line states in accordance with the rule shown in Table 5 below.
The above-defined IEEE 1394 standard provides necessary conditions for an interface for connecting an image-handling domestic equipment to a computer, so that a variety of equipments, such as audio or visual equipments or personal computers, can be easily connected over a sole cable in a home to construct a household network to permit it facilitated operation of the various equipments.
However, since the IEEE 1394 standard provides that the distance between the interconnected equipments, that is the inter-node cable length, is 4.5 m at the maximum, so that, if a network is to be constructed in a household across plural rooms, it is necessary to provide a large number of nodes only for cable relaying.
Also, if it is desired to elongate the cable without modifying the system of a physical layer in the IEEE 1394 standard, the cable needs to be increased in diameter, thus lowering workability in cable laying for the network, while the cable itself is expensive.
It is therefore an object of the present invention to provide a method and apparatus for transmission of digital serial data in which the inter-node cable length in a digital serial data interface, in which a bus using correct arbitration performed prior to data transfer as in the case of the IEEE 1394 standard, is elongated to enable long-distance transmission.
According to the present invention, there is provided a data transmission apparatus sending and receiving data and control codes including an input/output port, data conversion means for converting data for transmission from a n-bit code to a m-bit code and for converting the received data from the m-bit code to the n-bit code, control signal converting means for converting a transmission control signal for acquisition of use right of a transmission channel connected to the input/output port into a control code composed of a m-bit code other than a m-bit code allocated to data and for converting the received m-bit code into the control signal, scrambling means for performing scrambling on the m-bit control code received from the control signal converting means for reducing unneeded radiations to output the scrambled control code to the input/output port, and descrambling means for descrambling the scrambled signals received via the input/output port to output descrambled signals to the control signal converting means.
According to the present invention, there is also provided a data transmission method including a sending data conversion step for converting data for transmission from a n-bit code to a m-bit code, a reception data converting step for converting the received data from the m-bit code to the n-bit code, a transmission control signal converting step for converting a transmission control signal for acquisition of use right of a transmission channel connected to the input/output port into a control code composed of a m-bit code other than a m-bit code allocated to data and for converting the received m-bit code into the control signal, a scrambling step for performing scrambling on the m-bit control code received from the transmission control signal converting step for reducing unneeded radiations to output the scrambled control code to an input/output port and a descrambling step for descrambling the scrambled signals received via the input/output port.